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<p>Video Processing Subsystem configuration structure.  
 <a href="struct_x_v___hdmi_tx_ss___config.html#details">More...</a></p>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:ae5c834f5b6c2ce23e2012ff193a50d92"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss___config.html#ae5c834f5b6c2ce23e2012ff193a50d92">DeviceId</a></td></tr>
<tr class="memdesc:ae5c834f5b6c2ce23e2012ff193a50d92"><td class="mdescLeft">&#160;</td><td class="mdescRight">DeviceId is the unique ID of the device.  <a href="#ae5c834f5b6c2ce23e2012ff193a50d92">More...</a><br /></td></tr>
<tr class="separator:ae5c834f5b6c2ce23e2012ff193a50d92"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52882efb633aff03ac341a4e10c60cbf"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss___config.html#a52882efb633aff03ac341a4e10c60cbf">BaseAddress</a></td></tr>
<tr class="memdesc:a52882efb633aff03ac341a4e10c60cbf"><td class="mdescLeft">&#160;</td><td class="mdescRight">BaseAddress is the physical base address of the subsystem address range.  <a href="#a52882efb633aff03ac341a4e10c60cbf">More...</a><br /></td></tr>
<tr class="separator:a52882efb633aff03ac341a4e10c60cbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae8d24e2790d29a5deb80e9fe5db4be9f"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss___config.html#ae8d24e2790d29a5deb80e9fe5db4be9f">HighAddress</a></td></tr>
<tr class="memdesc:ae8d24e2790d29a5deb80e9fe5db4be9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">HighAddress is the physical MAX address of the subsystem address range.  <a href="#ae8d24e2790d29a5deb80e9fe5db4be9f">More...</a><br /></td></tr>
<tr class="separator:ae8d24e2790d29a5deb80e9fe5db4be9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9b69c2ce3b482768577982803318a1fe"><td class="memItemLeft" align="right" valign="top">XVidC_PixelsPerClock&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss___config.html#a9b69c2ce3b482768577982803318a1fe">Ppc</a></td></tr>
<tr class="memdesc:a9b69c2ce3b482768577982803318a1fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Supported Pixel per Clock.  <a href="#a9b69c2ce3b482768577982803318a1fe">More...</a><br /></td></tr>
<tr class="separator:a9b69c2ce3b482768577982803318a1fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0abdd1f7bd87e78a588d1dbb1222aeda"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss___config.html#a0abdd1f7bd87e78a588d1dbb1222aeda">MaxBitsPerPixel</a></td></tr>
<tr class="memdesc:a0abdd1f7bd87e78a588d1dbb1222aeda"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum Supported Color Depth.  <a href="#a0abdd1f7bd87e78a588d1dbb1222aeda">More...</a><br /></td></tr>
<tr class="separator:a0abdd1f7bd87e78a588d1dbb1222aeda"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f0f2c7dd28420c2940eeb225f65c70d"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss___config.html#a8f0f2c7dd28420c2940eeb225f65c70d">AxiLiteClkFreq</a></td></tr>
<tr class="memdesc:a8f0f2c7dd28420c2940eeb225f65c70d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI Lite Clock Frequency in Hz.  <a href="#a8f0f2c7dd28420c2940eeb225f65c70d">More...</a><br /></td></tr>
<tr class="separator:a8f0f2c7dd28420c2940eeb225f65c70d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab40463bab7c2d5c2964a863b9e66d68b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_tx_ss___sub_core.html">XV_HdmiTxSs_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss___config.html#ab40463bab7c2d5c2964a863b9e66d68b">HdcpTimer</a></td></tr>
<tr class="memdesc:ab40463bab7c2d5c2964a863b9e66d68b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#ab40463bab7c2d5c2964a863b9e66d68b">More...</a><br /></td></tr>
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<tr class="memitem:a318133034b909518b4f0b3aa36ded344"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_tx_ss___sub_core.html">XV_HdmiTxSs_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss___config.html#a318133034b909518b4f0b3aa36ded344">Hdcp14</a></td></tr>
<tr class="memdesc:a318133034b909518b4f0b3aa36ded344"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#a318133034b909518b4f0b3aa36ded344">More...</a><br /></td></tr>
<tr class="separator:a318133034b909518b4f0b3aa36ded344"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a69dac18d3c498ab36209848026908bb4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_tx_ss___sub_core.html">XV_HdmiTxSs_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss___config.html#a69dac18d3c498ab36209848026908bb4">Hdcp22</a></td></tr>
<tr class="memdesc:a69dac18d3c498ab36209848026908bb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#a69dac18d3c498ab36209848026908bb4">More...</a><br /></td></tr>
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<tr class="memitem:a8501750fab6e81cc2c7fb19e0e0a2126"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_tx_ss___sub_core.html">XV_HdmiTxSs_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss___config.html#a8501750fab6e81cc2c7fb19e0e0a2126">HdmiTx</a></td></tr>
<tr class="memdesc:a8501750fab6e81cc2c7fb19e0e0a2126"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#a8501750fab6e81cc2c7fb19e0e0a2126">More...</a><br /></td></tr>
<tr class="separator:a8501750fab6e81cc2c7fb19e0e0a2126"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a88af4667c06827b97fd7165c8d4be157"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_tx_ss___sub_core.html">XV_HdmiTxSs_SubCore</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx_ss___config.html#a88af4667c06827b97fd7165c8d4be157">Vtc</a></td></tr>
<tr class="memdesc:a88af4667c06827b97fd7165c8d4be157"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sub-core instance configuration.  <a href="#a88af4667c06827b97fd7165c8d4be157">More...</a><br /></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Video Processing Subsystem configuration structure. </p>
<p>Each subsystem device should have a configuration structure associated that defines the MAX supported sub-cores within subsystem </p>
</div><h2 class="groupheader">Field Documentation</h2>
<a id="a8f0f2c7dd28420c2940eeb225f65c70d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8f0f2c7dd28420c2940eeb225f65c70d">&#9670;&nbsp;</a></span>AxiLiteClkFreq</h2>

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          <td class="memname">u32 XV_HdmiTxSs_Config::AxiLiteClkFreq</td>
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<p>AXI Lite Clock Frequency in Hz. </p>

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<a id="a52882efb633aff03ac341a4e10c60cbf"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a52882efb633aff03ac341a4e10c60cbf">&#9670;&nbsp;</a></span>BaseAddress</h2>

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          <td class="memname">UINTPTR XV_HdmiTxSs_Config::BaseAddress</td>
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<p>BaseAddress is the physical base address of the subsystem address range. </p>

<p class="reference">Referenced by <a class="el" href="xv__hdmitxss_8h.html#ad8bb4a3d734b44a7618529c52a433cc5">XV_HdmiTxSs_CfgInitialize()</a>.</p>

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<a id="ae5c834f5b6c2ce23e2012ff193a50d92"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae5c834f5b6c2ce23e2012ff193a50d92">&#9670;&nbsp;</a></span>DeviceId</h2>

<div class="memitem">
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          <td class="memname">u16 XV_HdmiTxSs_Config::DeviceId</td>
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<p>DeviceId is the unique ID of the device. </p>

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<a id="a318133034b909518b4f0b3aa36ded344"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a318133034b909518b4f0b3aa36ded344">&#9670;&nbsp;</a></span>Hdcp14</h2>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_tx_ss___sub_core.html">XV_HdmiTxSs_SubCore</a> XV_HdmiTxSs_Config::Hdcp14</td>
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<p>Sub-core instance configuration. </p>

<p class="reference">Referenced by <a class="el" href="group__v__hdmitxss.html#ga2c1e0df6df7d8d7618d3bdde8eb86923">XV_HdmiTxSs_SubcoreInitVtc()</a>.</p>

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<a id="a69dac18d3c498ab36209848026908bb4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a69dac18d3c498ab36209848026908bb4">&#9670;&nbsp;</a></span>Hdcp22</h2>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_tx_ss___sub_core.html">XV_HdmiTxSs_SubCore</a> XV_HdmiTxSs_Config::Hdcp22</td>
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<p>Sub-core instance configuration. </p>

<p class="reference">Referenced by <a class="el" href="group__v__hdmitxss.html#ga2c1e0df6df7d8d7618d3bdde8eb86923">XV_HdmiTxSs_SubcoreInitVtc()</a>.</p>

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<a id="ab40463bab7c2d5c2964a863b9e66d68b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab40463bab7c2d5c2964a863b9e66d68b">&#9670;&nbsp;</a></span>HdcpTimer</h2>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_tx_ss___sub_core.html">XV_HdmiTxSs_SubCore</a> XV_HdmiTxSs_Config::HdcpTimer</td>
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<p>Sub-core instance configuration. </p>

<p class="reference">Referenced by <a class="el" href="group__v__hdmitxss.html#ga2c1e0df6df7d8d7618d3bdde8eb86923">XV_HdmiTxSs_SubcoreInitVtc()</a>.</p>

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<a id="a8501750fab6e81cc2c7fb19e0e0a2126"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8501750fab6e81cc2c7fb19e0e0a2126">&#9670;&nbsp;</a></span>HdmiTx</h2>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_tx_ss___sub_core.html">XV_HdmiTxSs_SubCore</a> XV_HdmiTxSs_Config::HdmiTx</td>
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<p>Sub-core instance configuration. </p>

<p class="reference">Referenced by <a class="el" href="group__v__hdmitxss.html#ga23588544c59439321e952b7b4a2c6445">XV_HdmiTxSs_SubcoreInitHdmiTx()</a>.</p>

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<a id="ae8d24e2790d29a5deb80e9fe5db4be9f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae8d24e2790d29a5deb80e9fe5db4be9f">&#9670;&nbsp;</a></span>HighAddress</h2>

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          <td class="memname">UINTPTR XV_HdmiTxSs_Config::HighAddress</td>
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<p>HighAddress is the physical MAX address of the subsystem address range. </p>

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<a id="a0abdd1f7bd87e78a588d1dbb1222aeda"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0abdd1f7bd87e78a588d1dbb1222aeda">&#9670;&nbsp;</a></span>MaxBitsPerPixel</h2>

<div class="memitem">
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          <td class="memname">u8 XV_HdmiTxSs_Config::MaxBitsPerPixel</td>
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<p>Maximum Supported Color Depth. </p>

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<a id="a9b69c2ce3b482768577982803318a1fe"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9b69c2ce3b482768577982803318a1fe">&#9670;&nbsp;</a></span>Ppc</h2>

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          <td class="memname">XVidC_PixelsPerClock XV_HdmiTxSs_Config::Ppc</td>
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<p>Supported Pixel per Clock. </p>

<p class="reference">Referenced by <a class="el" href="xv__hdmitxss_8h.html#a21e9e6ec102c13e90db7c1681031eb37">XV_HdmiTxSs_SetPpc()</a>, and <a class="el" href="xv__hdmitxss_8h.html#a893af41ef8123dbcc6c697e211656d6e">XV_HdmiTxSs_SetStream()</a>.</p>

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<h2 class="memtitle"><span class="permalink"><a href="#a88af4667c06827b97fd7165c8d4be157">&#9670;&nbsp;</a></span>Vtc</h2>

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<p>Sub-core instance configuration. </p>

<p class="reference">Referenced by <a class="el" href="group__v__hdmitxss.html#ga2c1e0df6df7d8d7618d3bdde8eb86923">XV_HdmiTxSs_SubcoreInitVtc()</a>.</p>

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